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This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate current scales the gate voltage, a function of time, to a function of coulombs. The slope of the generated response reflects the active device capacitance as it varies during the switching transition . Gate charge measurements are useful for characterizing the large signal switching performance of power MOS and IGBT devices. Developed over a four year span by the JEDEC JC-25 Committee, the method defines a repeatable means of measuring the widely published Qgd charge values.
Author | EIA |
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Editor | EIA |
Document type | Standard |
Format | File |
Confirmation date | 2002-10-01 |
ICS | 31.080.01 : Semiconductor devices in general
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Number of pages | 14 |
Modify | EIA JESD 24 (1985)
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Year | 1990 |
Document history | |
Country | USA |
Keyword | EIA JESD 24;EIA 24;EIA 24.2;24;EIA JESD24-2 |