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EIA JESD 35-A:2001

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EIA JESD 35-A:2001

Procedure for the Wafer-Level Testing of Thin Dielectrics

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The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown.

Author EIA
Editor EIA
Document type Standard
Format File
ICS 31.140 : Piezoelectric devices
Number of pages 47
Replace EIA JESD 35 (1992)
Modified by EIA JESD 35-2 (1996-02)
EIA JESD 35-1 (1995-09)
Year 2001
Document history EIA JESD 35-A (2001-04)
Country USA
Keyword EIA JESD 35;EIA 35;35;EIA JESD35-A