EIA JEP 150.01:2013

This publication contains a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products, in particular leadless chip carriers, ball grid array (BGA) packages, direct chip attach die and packages with exposed pads that are attached to the PWB for thermal considerations. Assembly level testing may not be a prerequisite for device qualification; however, if the effect of assembly conditions on the component is not known, there could be reliability concerns for that component that are not evident in component level testing. As such, it is recommended that assembly level testing be performed to determine if there are any adverse effects on that component due to its assembly to a PWB. These reliability stress tests have been found capable of stimulating and precipitating failures in assembled components in an accelerated manner, but these tests should not be used indiscriminately. Each qualification should be examined for: a) Any potential new and unique failure mechanisms. b) Any situation where these tests and/or conditions may induce false failures. In either case the set of reliability requirements, tests and/or conditions should be appropriately modified to properly comprehend the new situations. This document does not relieve the supplier of the responsibility to meet internal or customer specified qualification programs.